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1/64 may 2003 m36w832te m36w832be 32 mbit (2mb x16, boot block) flash memory and 8 mbit (512kb x16) sram, multiple memory product features summary n supply voltage Cv ddf = 2.7v to 3.3v Cv dds = v ddqf = 2.7v to 3.3v Cv ppf = 12v for fast program (optional) n access times: 70ns and 85ns n low power consumption n electronic signature C manufacturer code: 20h C top device code, m36w832te: 88bah C bottom device code, m36w832be: 88bbh flash memory n 32 mbit (2mb x16) boot block C 8 x 4 kword parameter blocks (top or bottom location) n programming time C 10s typical C double word programming option C quadruple word programming option n block locking C all blocks locked at power up C any combination of blocks can be locked Cwpf for block lock-down n automatic standby mode n program and erase su spend n 100,000 program/erase cycles per block n common flash interface n security C 128 bit user programmable otp cells C 64 bit unique device identifier figure 1. packages sram n 8 mbit (512kb x 16) n access time: 70ns n low v dds data retention: 1.5v n power down features using two chip enable inputs fbga stacked lfbga66 (za) 12 x 8mm
m36w832te, m36w832be 2/64 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. lfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 address inputs (a0-a18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 address inputs (a19-a20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 data input/output (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash chip enable (ef). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash output enable (gf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash write enable (wf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash write protect (wpf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 flash reset (rpf). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sram chip enable (e1s, e2s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sram write enable (ws). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 sram output enable (gs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 sram upper byte enable (ubs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sram lower byte enable (lbs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ddf supply voltage (2.7v to 3.3v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ddqf and v dds supply voltage (2.7v to 3.3v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ppf program supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 v ssf and v sss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. main operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 flash memory component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. flash block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. flash security block and protection register memory map . . . . . . . . . . . . . . . . . . . 12 sram component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. sram block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 flash bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 flash command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. flash command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read memory array command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/64 m36w832te, m36w832be read electronic signature command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 double word program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 quadruple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 4. flash commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. flash read electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. flash read block lock signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. flash read protection register and lock register . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. flash program, erase times and program/erase endurance cycles . . . . . . . . . . . . 20 flash block locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reading a blocks lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 lock-down state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. block lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. protection status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program status (bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 v ppf status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 block protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 reserved (bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. flash status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 sram operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 standby/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
m36w832te, m36w832be 4/64 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 table 14. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 10. flash read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 16. flash read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 11. flash write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17. flash write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12. flash write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 18. flash write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13. flash power-up and reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. flash power-up and reset ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14. sram read mode ac waveforms, address controlled with ubs = lbs = v il . . . . . . 36 figure 15. sram read ac waveforms, gs controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. sram standby ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 17. sram write ac waveforms, e1s or e2s controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 20. sram read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 18. sram write ac waveforms, ws controlled, gs high during write . . . . . . . . . . . . . . . 38 figure 19. sram write ac waveforms, ws controlled with gs low . . . . . . . . . . . . . . . . . . . . . . 38 figure 20. sram write cycle waveform, ubs and lbs controlled gs low, . . . . . . . . . . . . . . . . 39 table 21. sram write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 21. sram low v dds data retention ac waveforms, e1s controlled . . . . . . . . . . . . . . . . 41 figure 22. sram low v dds data retention ac waveforms, e2s controlled . . . . . . . . . . . . . . . . 41 table 22. sram low v dds data retention characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 23. stacked lfbga66 12x8mm, 8x8 array, 0.8mm pitch, bottom view package outline. . 42 table 23. stacked lfbga66, 12x8mm, 8x8 ball array, 0.8mm pitch, package mechanical data . 42 figure 24. stacked lfbga66 daisy chain - package connections (top view through package) . 43 figure 25. stacked lfbga66 daisy chain - pcb connections proposal (top view through package)44 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 table 25. daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 appendix a. flash memory block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 26. top boot block addresses, m36w832te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 27. bottom boot block addresses, m36w832be . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 appendix b. common flash interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 28. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 29. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 30. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5/64 m36w832te, m36w832be table 31. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 32. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 33. security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 appendix c. flash memory flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . 53 figure 26. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 27. double word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 28. quadruple word program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 29. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 56 figure 30. erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 31. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . 58 figure 32. locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 33. protection register program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . 60 appendix d. flash memory command interface and program/erase controller state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 34. write state machine current/next, sheet 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 35. write state machine current/next, sheet 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 36. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
m36w832te, m36w832be 6/64 summary description the m36w832te is a low voltage multiple memo- ry product which combines two memory devices; a 32 mbit boot block flash memory and an 8 mbit sram. recommended operating conditions do not allow both the flash and the sram to be ac- tive at the same time. the memory is offered in a stacked lfbga66 (12x8mm, 0.8 mm pitch) package and is supplied with all the bits erased (set to 1). figure 2. logic diagram table 1. signal names ai90161b 21 a0-a20 ef dq0-dq15 v ddf m36w832te m36w832be gf v ssf 16 wf rpf wpf v ddqf e1s e2s gs ws ubs lbs v sss v ppf v dds a0-a18 address inputs common to the flash and sram chips a19-a20 address inputs for flash chip only dq0-dq15 data input/output v ddf flash power supply v ddqf flash power supply for i/o buffers v ppf flash optional supply voltage for fast program & erase v ssf flash ground v dds sram power supply v sss sram ground nc not connected internally flash control functions ef chip enable input gf output enable input wf write enable input rpf reset input wpf write protect input sram control functions e1s , e2s chip enable inputs gs output enable input ws write enable input ubs upper byte enable input lbs lower byte enable input
7/64 m36w832te, m36w832be figure 3. lfbga connections (top view through package) ai90162b a 8 7 6 5 4 3 2 1 e b f a12 a13 a11 a20 nc nc e2s dq12 v sss a2 a3 a6 a7 a18 ef a0 a4 nc nc dq4 ws dq15 a9 a16 dq6 dq13 nc wf a8 a10 a5 nc v ssf a17 rpf a15 a14 nc nc v ddf e1s a1 nc nc gf v dds dq7 dq5 dq14 nc v ssf v ddqf 12 11 10 9 c dq10 dq11 a19 wpf v ppf dq3 dq2 d dq8 dq9 gs lbs ubs dq1 dq0 g h
m36w832te, m36w832be 8/64 signal descriptions see figure 2 logic diagram and table 1,signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a18). addresses a0-a18 are common inputs for the flash and the sram components. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they con- trol the commands sent to the command interface of the internal state machine. the flash memory is accessed through the chip enable ( ef ) and write enable (wf ) signals, while the sram is accessed through two chip enable signals (e1s and e2s) and the write enable signal (ws ). address inputs (a19-a20). addresses a19-a20 are inputs for the flash component only. the flash memory is accessed through the chip en- able (ef ) and write enable (wf ) signals data input/output (dq0-dq15). the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a write bus operation. flash chip enable (ef ). the chip enable input activates the flash memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the standby level. flash output enable (gf ). the output enable controls the data outputs during the bus read op- eration of the flash memory. flash write enable ( wf ). the write enable controls the bus write operation of the flash memorys command interface. the data and ad- dress inputs are latched on the rising edge of chip enable, ef , or write enable, wf , whichever oc- curs first. flash write protect (wpf ). write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the block cannot be changed. when write protect is at v ih , the lock-down is disabled and the block can be locked or unlocked. (refer to table 6, read protection register and protection register lock). flash reset (rpf ). the reset input provides a hardware reset of the flash memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. after reset all blocks are in the locked state. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters read array mode, but a negative transition of chip enable or a change of the address is re- quired to ensure valid data outputs. sram chip enable (e1s , e2s). the chip en- able inputs activate the sram memory control logic, input buffers and decoders. e1s at v ih or e2s at v il deselects the memory and reduces the power consumption to the standby level. e1s and e2s can also be used to control writing to the sram memory array, while ws remains at v il. it is not allowed to set ef at v il, e1s at v il and e2s at v ih at the same time. sram write enable (ws ). the write enable in- put controls writing to the sram memory array. ws is active low. sram output enable (gs) . the output enable gates the outputs through the data buffers during a read operation of the sram memory. gs is ac- tive low. sram upper byte enable (ubs) . the upper byte enable enables the upper bytes for sram (dq8-dq15). ubs is active low. sram lower byte enable (lbs ). the lower byte enable enables the lower bytes for sram (dq0-dq7). lbs is active low. v ddf supply voltage (2.7v to 3.3v). v ddf pro- vides the power supply to the internal core of the flash memory device. it is the main power supply for all operations (read, program and erase). v ddqf and v dds supply voltage (2.7v to 3.3v). v ddqf provides the power supply for the flash memory i/o pins and v dds provides the power supply for the sram control pins. this allows all outputs to be powered independently of the flash core power supply, v ddf . v ddqf can be tied to v dds v ppf program supply voltage. v ppf is both a control input and a power supply pin for the flash memory. the two functions are selected by the voltage range applied to the pin. the supply volt- age v ddf and the program supply voltage v ppf can be applied in any order. if v ppf is kept in a low voltage range (0v to 3.6v) v ppf is seen as a control input. in this case a volt- age lower than v pplk gives an absolute protection against program or erase, while v ppf > v pp1 en- ables these functions (see table 15, dc charac- teristics for the relevant values). v ppf is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect on program or erase, however for double or quadruple word program the results are uncertain. if v ppf is in the range 11.4v to 12.6v it acts as a power supply pin. in this condition v ppf must be stable until the program/erase algorithm is com- pleted (see table 17 and 18).
9/64 m36w832te, m36w832be v ssf and v sss ground. v ssf and v sss are the ground reference for all voltage measurements in the flash and sram chips, respectively. note: each device in a system should have v d- df , v ddqf and v ppf decoupled with a 0.1f ca- pacitor close to the pin. see figure 9, ac measurement load circuit. the pcb trace widths should be sufficient to carry the re- quired v ppf program and erase currents. functional description the flash and sram components have separate power supplies and grounds and are distinguished by three chip enable inputs: ef for the flash mem- ory and, e1s and e2s for the sram. recommended operating conditions do not allow both the flash and the sram to be in active mode at the same time. the most common example is simultaneous read operations on the flash and the sram which would result in a data bus con- tention. therefore it is recommended to put the sram in the high impedance state when reading the flash and vice versa (see table 2 main oper- ation modes for details). figure 4. functional block diagram ai90163 flash memory 32 mbit (x16) v ssf ef gf wf rpf wpf e1s e2s gs ws ubs lbs dq0-dq15 v ddf v ppf a19-a20 a0-a18 sram 8 mbit (x16) v sss v dds v ddqf
m36w832te, m36w832be 10/64 table 2. main operation modes note: x = v il or v ih , v ppfh = 12v 5%. operation mode ef gf wf rpf wpf v ppf e1s e2s ws gs ubs lbs dq15-dq8 dq7-dq0 flash memory read v il v il v ih v ih x don't care sram must be disabled data output write v il v ih v il v ih x v ddf or v ppfh sram must be disabled data input block locking v il xx v ih v il don't care sram must be disabled x standby v ih xx v ih x don't care any sram mode is allowed hi-z reset x x x v il x don't care any sram mode is allowed hi-z output disable v il v ih v ih v ih x don't care any sram mode is allowed hi-z sram read flash must be disabled xxv ih v il v il v il data out v il v ih v ih v il v ih v il hi-z data out v il v ih v ih v il v il v ih data out hi-z write flash must be disabled v il v ih v il x v il v il data in v il v ih v il x v ih v il hi-z data in v il v ih v il x v il v ih data in hi-z standby/ power down any flash mode is allowable v ih x x x x x hi-z x v il xx v ih v ih hi-z data retention any flash mode is allowable v ih x x x x x hi-z x v il x x x x hi-z output disable any flash mode is allowable v il v ih v ih v ih x x hi-z
11/64 m36w832te, m36w832be flash memory component the flash memory is a 32 mbit (2 mbit x 16) device that can be erased electrically at block level and programmed in-system on a word-by-word basis. these operations can be performed using a single low voltage (2.7 to 3.6v) supply. v ddqf allows to drive the i/o pin down to 1.65v. an optional 12v v ppf power supply is provided to speed up cus- tomer programming. the device features an asymmetrical blocked ar- chitecture with an array of 71 blocks: 8 parameter blocks of 4 kwords and 63 main blocks of 32 kwords. the m36w832te has the parameter blocks at the top of the memory address space while the m36w832be locates the parameter blocks starting from the bottom. the memory maps are shown in figure 5, block addresses. the flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling in- stant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any acciden- tal programming or erasure. there is an additional hardware protection against program and erase. when v ppf v pplk all blocks are protected against program or erase. all blocks are locked at power up. each block can be erased separately. erase can be suspended in order to perform either read or program in any other block and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles. the device includes a protection register to in- crease the protection of a system design. the pro- tection register is divided into two segments, the first is a 64 bit area which contains a unique device number written by st, while the second is a 128 bit area, one-time-programmable by the user. the user programmable segment can be permanently protected. figure 6, shows the flash security block and protection register memory map. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller takes care of the tim- ings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. figure 5. flash block addresses note: also see appendix a, tables 26 and 27 for a full listing of the flash block addresses. ai90164 4 kwords 1fffff 1ff000 32 kwords 00ffff 008000 32 kwords 007fff 000000 top boot block addresses 4 kwords 1f8fff 1f8000 32 kwords 1f0000 1f7fff total of 8 4 kword blocks total of 63 32 kword blocks 4 kwords 1fffff 1f8000 32 kwords 32 kwords 000fff 000000 bottom boot block addresses 4 kwords 1f7fff 00ffff 32 kwords 1f0000 008000 total of 63 32 kword blocks total of 8 4 kword blocks 007fff 007000
m36w832te, m36w832be 12/64 figure 6. flash security block and protection register memory map note: 1. bit 2 of the protection register lock must not be programmed to 0. ai90165b user programmable otp unique device number protection register lock 2 (1) 10 8ch 85h 84h 81h 80h protection register
13/64 m36w832te, m36w832be sram component the sram is an 8 mbit asynchronous random ac- cess memory which features a super low voltage operation and low current consumption with an ac- cess time of 70ns in all conditions. the memory operations can be performed using a single low voltage supply, 2.7v to 3.3v, which is the same as the flash voltage supply. figure 7. sram block diagram data in drivers 512kb x 16 ram array 2048 x 4096 column decoder row decoder a0-a10 ws ubs lbs sense amps a11-a18 power-down circuit dq0-dq7 dq8-dq15 gs ubs lbs ai 07964 e1s e2s e1s e2s
m36w832te, m36w832be 14/64 operating modes flash bus operations there are six standard bus operations that control the device. these are bus read, bus write, out- put disable, standby, automatic standby and re- set. see table 2, main operation modes, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. read. read bus operations are used to output the contents of the memory array, the electronic signature, the status register and the common flash interface. both chip enable and output en- able must be at v il in order to perform a read op- eration. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read de- pends on the previous command written to the memory (see command interface section). see figure 10, flash read mode ac waveforms, and table 16, flash read ac characteristics, for de- tails of when the output becomes valid. read mode is the default state of the device when exiting reset or after power-up. write. bus write operations write commands to the memory or latch input data to be programmed. a write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. see figures 11 and 12, flash write ac wave- forms, and tables 17 and 18, write ac character- istics, for details of the timing requirements. output disable. the data outputs are high im- pedance when the output enable is at v ih . standby. standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. the memory is in stand-by when chip enable is at v ih and the device is in read mode. the power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the de- vice enters standby mode when finished. automatic standby. automatic standby pro- vides a low power consumption state during read mode. following a read operation, the device en- ters automatic standby after 150ns of bus inactiv- ity even if chip enable is low, v il , and the supply current is reduced to i dd1 . the data inputs/out- puts will still output data if a bus read operation is in progress. reset. during reset mode when output enable is low, v il , the memory is deselected and the out- puts are high impedance. the memory is in reset mode when reset is at v il . the power consump- tion is reduced to the standby level, independently from the chip enable, output enable or write en- able inputs. if reset is pulled to v ssf during a pro- gram or erase, this operation is aborted and the memory content is no longer valid.
15/64 m36w832te, m36w832be flash command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. an internal program/erase controller han- dles all timings and verifies the correct execution of the program and erase commands. the pro- gram/erase controller provides a status register whose output may be read at any time during, to monitor the progress of the operation, or the pro- gram/erase states. see table 4, command codes, for a summary of the commands and see appendix 31, table 34, write state machine cur- rent/next, for a summary of the command inter- face. the command interface is reset to read mode when power is first applied, when exiting from re- set or whenever v ddf is lower than v lko . com- mand sequences must be followed exactly. any invalid combination of commands will reset the de- vice to read mode. refer to table 3, flash com- mand codes, in conjunction with the following text descriptions. table 3. flash command codes read memory array command. the read command returns the memory to its read mode. one bus write cycle is required to issue the read memory array command and return the memory to read mode. subsequent read operations will read the addressed location and output the data. when a device reset occurs, the memory defaults to read mode. read status register command. the status register indicates when a program or erase oper- ation is complete and the success or failure of the operation itself. issue a read status register command to read the status registers contents. subsequent bus read operations read the status register at any address, until another command is issued. see table 11, status register bits, for de- tails on the definitions of the bits. the read status register command may be is- sued at any time, even during a program/erase operation. any read attempt during a program/ erase operation will automatically output the con- tent of the status register. read electronic signature command. the read electronic signature command reads the manufacturer and device codes and the block locking status, or the protection register. the read electronic signature command consists of one write cycle, a subsequent read will output the manufacturer code, the device code, the block lock and lock-down status, or the protec- tion and lock register. see tables 5, 6 and 7 for the valid address. read cfi query command. the read query command is used to read data from the common flash interface (cfi) memory area, allowing pro- gramming equipment or applications to automati- cally match their interface to the characteristics of the device. one bus write cycle is required to is- sue the read query command. once the com- mand is issued subsequent bus read operations read from the common flash interface memory area. see appendix b, common flash interface, tables 28, 29, 30, 31, 32 and 33 for details on the information contained in the common flash inter- face memory area. block erase command. the block erase com- mand can be used to erase a block. it sets all the bits within the selected block to 1. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write cycles are required to issue the command. n the first bus cycle sets up the erase command. hex code command 01h block lock confirm 10h program 20h erase 2fh block lock-down confirm 30h double word program 40h program 50h clear status register 55h reserved 56h quadruple word program 60h block lock, block unlock, block lock- down 70h read status register 90h read electronic signature 98h read cfi query b0h program/erase suspend c0h protection register program d0h program/erase resume, block unlock confirm ffh read memory array
m36w832te, m36w832be 16/64 n the second latches the block address in the internal state machine and starts the program/ erase controller. if the second bus cycle is not write erase confirm (d0h), status register bits b4 and b5 are set and the command aborts. erase aborts if reset turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the block must be erased again. during erase operations the memory will accept the read status register command and the pro- gram/erase suspend command, all other com- mands will be ignored. typical erase times are given in table 8, flash program, erase times and program/erase endurance cycles. see appendix c, figure 30, erase flowchart and pseudo code, for a suggested flowchart for using the erase command. program command. the memory array can be programmed word-by-word. two bus write cycles are required to issue the program command. n the first bus cycle sets up the program command. n the second latches the address and the data to be written and starts the program/erase controller. during program operations the memory will ac- cept the read status register command and the program/erase suspend command. typical pro- gram times are given in table 8, flash program, erase times and program/erase endurance cy- cles. programming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and repro- grammed. see appendix c, figure 26, program flowchart and pseudo code, for the flowchart for using the program command. double word program command. this feature is offered to improve the programming throughput, writing a page of two adjacent words in paral- lel.the two words must differ only for the address a0. programming should not be attempted when v ppf is not at v pph . three bus write cycles are necessary to issue the double word program command. n the first bus cycle sets up the double word program command. n the second bus cycle latches the address and the data of the first word to be written. n the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. read operations output the status register con- tent after the programming has started. program- ming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program opera- tion is aborted, the block containing the memory location must be erased and reprogrammed. see appendix c, figure 27, double word pro- gram flowchart and pseudo code, for the flow- chart for using the double word program command. quadruple word program command. this feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel.the four words must differ only for the addresses a0 and a1. programming should not be attempted when v ppf is not at v pph . five bus write cycles are necessary to issue the quadruple word program command. n the first bus cycle sets up the quadruple word program command. n the second bus cycle latches the address and the data of the first word to be written. n the third bus cycle latches the address and the data of the second word to be written. n the fourth bus cycle latches the address and the data of the third word to be written. n the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. read operations output the status register con- tent after the programming has started. program- ming aborts if reset goes to v il . as data integrity cannot be guaranteed when the program opera- tion is aborted, the block containing the memory location must be erased and reprogrammed. see appendix c, figure 28, quadruple word pro- gram flowchart and pseudo code, for the flow- chart for using the quadruple word program command. clear status register command. the clear status register command can be used to reset bits 1, 3, 4 and 5 in the status register to 0. one bus write cycle is required to issue the clear sta- tus register command. the bits in the status register do not automatical- ly return to 0 when a new program or erase com- mand is issued. the error bits in the status register should be cleared before attempting a new program or erase command. program/erase suspend command. the pro- gram/erase suspend command is used to pause a program or erase operation. one bus write cycle is required to issue the program/erase command and pause the program/erase controller. during program/erase suspend the command in- terface will accept the program/erase resume,
17/64 m36w832te, m36w832be read array, read status register, read electron- ic signature and read cfi query commands. ad- ditionally, if the suspend operation was erase then the program, double word program, quadruple word program, block lock, block lock-down or protection program commands will also be ac- cepted. the block being erased may be protected by issuing the block protect, block lock or protec- tion program commands. when the program/ erase resume command is issued the operation will complete. only the blo cks not being erased may be read or programmed correctly. during a program/erase suspend, the device can be placed in a pseudo-standby mode by taking chip enable to v ih . program/erase is aborted if reset turns to v il . see appendix c, figure 29, program or double word program suspend & resume flowchart and pseudo code, and figure 31, erase suspend & resume flowchart and pseudo code for flow- charts for using the program/erase suspend com- mand. program/erase resume command. the pro- gram/erase resume command can be used to re- start the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the com- mand. once the command is issued subsequent bus read operations read the status register. see appendix c, figure 29, program or double word program suspend & resume flowchart and pseudo code, and figure 31, erase suspend & resume flowchart and pseudo code for flow- charts for using the program/erase resume com- mand. protection register program command. the protection register program command is used to program the 128 bit user one-time-programma- ble (otp) segment of the protection register. the segment is programmed 16 bits at a time. when shipped all bits in the segment are set to 1. the user can only program the bits to 0. two write cycles are required to issue the protec- tion register program command. n the first bus cycle sets up the protection register program command. n the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the segment can be protected by programming bit 1 of the protection lock register (see figure 6, flash security block and protection register memory map). attempting to program a previously protected protection register will result in a status register error. the protection of the protection register is not reversible. the protection register program cannot be sus- pended. block lock command. the block lock com- mand is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked at power-up or reset. two bus write cycles are required to issue the block lock command. n the first bus cycle sets up the block lock command. n the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table. 10 shows the protection status after issuing a block lock command. the block lock bits are volatile, once set they re- main set until a hardware reset or power-down/ power-up. they are cleared by a blocks unlock command. refer to the section, block locking, for a detailed explanation. block unlock command. the blocks unlock command is used to unlock a block, allowing the block to be programmed or erased. two bus write cycles are required to issue the blocks unlock command. n the first bus cycle sets up the block unlock command. n the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. table. 10 shows the protection status after issuing a block unlock command. refer to the flash block locking section, for a detailed explanation. block lock-down command. a locked block cannot be programmed or erased, or have its pro- tection status changed when wpf is low, v il . when wpf is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock command. two bus write cycles are required to issue the block lock-down command. n the first bus cycle sets up the block lock command. n the second bus write cycle latches the block address. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. table. 10 shows the protection sta- tus after issuing a block lock-down command.
m36w832te, m36w832be 18/64 refer to the flash block locking section for a de- tailed explanation. table 4. flash commands note: x = don't care. 1. the signature addresses are listed in tables 5, 6 and 7. 2. addr 1 and addr 2 must be consecutive addresses differing only for a0. 3. program addresses 1 and 2 must be consecutive addresses differing only for a0. 4. program addresses 1,2,3 and 4 must be consecutive addresses differing only for a0 and a1. 5. 55h is reserved. 6. to be characterized. commands cycles bus write operations 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle op. add data op. add data op. add data op. add data op. add data read memory array 1+ write x ffh read ra rd read status register 1+ write x 70h read x srd read electronic signature 1+ write x 90h read sa (2) idh read cfi query 1+ write x 98h read qa qd erase 2 write x 20h write ba d0h program 2 write x 40h or 10h write pa pd double word program (3) 3 write x 30h write pa1 pd1 write pa2 pd2 quadruple word program (4) 5write x 56h (6) write pa1 pd1 write pa2 pd2 write pa3 pd3 write pa4 pd4 clear status register 1 write x 50h program/erase suspend 1write x b0h program/erase resume 1write x d0h block lock 2 write x 60h write ba 01h block unlock 2 write x 60h write ba d0h block lock-down 2 write x 60h write ba 2fh protection register program 2 write x c0h write pra prd
19/64 m36w832te, m36w832be table 5. flash read electronic signature note: rpf = v ih . table 6. flash read block lock signature note: 1. a locked block can be protected "dq0 = 1" or unprotected "dq0 = 0"; see block locking section. table 7. flash read protection register and lock register code device ef gf wf a0 a1 a2-a7 a8-a11 a12-a20 dq0-dq7 dq8-dq15 manufacture code v il v il v ih v il v il 0 don't care 20h 00h v il device code m36w832te v il v il v ih v ih v il 0 don't care bah 88h v il m36w832be v il v il v ih v ih v il 0 don't care bbh 88h v il block status ef gf wf a0 a1 a2-a7 a8-a20 a12-a20 dq0 dq1 dq2-dq15 locked block v il v il v ih v il v ih 0 don't care block address 1 0 00h unlocked block v il v il v ih v il v ih 0 don't care block address 0 0 00h locked-down block v il v il v ih v il v ih 0 don't care block address x (1) 1 00h word ef gf wf a0-a7 a8-a20 dq0 dq1 dq2 dq3-dq7 dq8-dq15 lock v il v il v ih 80h don't care don't care otp prot. data don't care see note (1) don't care don't care unique id 0 v il v il v ih 81h don't care id data id data id data id data id data unique id 1 v il v il v ih 82h don't care id data id data id data id data id data unique id 2 v il v il v ih 83h don't care id data id data id data id data id data unique id 3 v il v il v ih 84h don't care id data id data id data id data id data otp 0 v il v il v ih 85h don't care otp data otp data otp data otp data otp data otp 1 v il v il v ih 86h don't care otp data otp data otp data otp data otp data otp 2 v il v il v ih 87h don't care otp data otp data otp data otp data otp data otp 3 v il v il v ih 88h don't care otp data otp data otp data otp data otp data
m36w832te, m36w832be 20/64 table 8. flash program, erase times and program/erase endurance cycles note: 1. typical time to program a main or parameter block using the double word program and the quadruple word program commands respectively. parameter test conditions flash device unit min typ max word program v ppf = v ddf 10 200 s double word program v ppf = 12v 5% 10 200 s quadruple word program v ppf = 12v 5% 10 200 s main block program v ppf = 12v 5% 0.16/0.08 (1) 5s v ppf = v ddf 0.32 5 s parameter block program v ppf = 12v 5% 0.02/0.01 (1) 4s v ppf = v ddf 0.04 4 s main block erase v ppf = 12v 5% 110s v ppf = v dd v ddf 110s parameter block erase v ppf = 12v 5% 0.4 10 s v ppf = v ddf 0.4 10 s program/erase cycles (per block) 100,000 cycles
21/64 m36w832te, m36w832be flash block locking the flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. n lock/unlock - this first level allows software- only control of block locking. n lock-down - this second level requires hardware interaction before locking can be changed. n v ppf v pplk - the third level offers a complete hardware protection against program and erase on all blocks. the protection status of each block can be set to locked, unlocked, and lock-down. table 10, de- fines all of the possible protection states (wpf , dq1, dq0), and appendix c, figure 32, shows a flowchart for the locking operations. reading a blocks lock status. the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode write 90h to the device. subsequent reads at the address specified in table 6, will output the protec- tion status of that block. the lock status is repre- sented by dq0 and dq1. dq0 indicates the block lock/unlock status and is set by the lock com- mand and cleared by the unlock command. it is also automatically set when entering lock-down. dq1 indicates the lock-down status and is set by the lock-down command. it cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. locked state. the default status of all blocks on power-up or after a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from any program or erase. any pro- gram or erase operations attempted on a locked block will return an error in the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software commands. an unlocked block can be locked by issuing the lock command. unlocked state. unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered- down. the status of an unlocked block can be changed to locked or locked-down using the ap- propriate software commands. a locked block can be unlocked by issuing the unlock command. lock-down state. blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using soft- ware commands alone. a locked or unlocked block can be locked-down by issuing the lock- down command. locked-down blocks revert to the locked state when the device is reset or pow- ered-down. the lock-down function is dependent on the wpf input pin. when wpf =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from pro- gram, erase and protection status changes. when wpf =1 (v ih ) the lock-down function is disabled (1,1,1) and locked-down blocks can be individu- ally unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. these blocks can then be relocked (1,1,1) and unlocked (1,1,0) as desired while wpf remains high. when wpf is low , blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any changes made while wpf was high. device reset or power-down resets all blocks , including those in lock-down, to the locked state. locking operations during erase suspend. changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase opera- tion, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after complet- ing any desired lock, read, or program operations, resume the erase operation with the erase re- sume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. refer to appendix d, com- mand interface and program/erase controller state, for detailed information on which com- mands are valid during erase suspend.
m36w832te, m36w832be 22/64 table 9. block lock status table 10. protection status note: 1. the lock status is defined by the write protect pin and by dq1 (1 for a locked-down block) and dq0 (1 for a locked block) a s read in the read electronic signature command with a1 = v ih and a0 = v il . 2. all blocks are locked at power-up, so the default configuration is 001 or 101 according to wpf status. 3. a wpf transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. item address data block lock configuration xx002 lock block is unlocked dq0=0 block is locked dq0=1 block is locked-down dq1=1 current lock status (1) (wpf , dq1, dq0) next lock status (1) (wpf , dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wpf transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)
23/64 m36w832te, m36w832be flash status register the status register provides information on the current or previous program or erase operation. the various bits convey information and errors on the operation. to read the status register the read status register command can be issued, re- fer to read status register command section. to output the contents, the status register is latched on the falling edge of the chip enable or output enable signals, and can be read until chip enable or output enable returns to v ih . either chip en- able or output enable must be toggled to update the latched data. bus read operations from any address always read the status register during program and erase operations. the bits in the status register are summarized in table 11, status register bits. refer to table 11 in conjunction with the following text descriptions. program/erase controller status (bit 7). the pro- gram/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is low (set to 0), the program/erase controller is active; when the bit is high (set to 1), the pro- gram/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high . during program, erase, operations the program/ erase controller status bit can be polled to find the end of the operation. other bits in the status reg- ister should not be tested until the program/erase controller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status, v ppf status and block lock status bits should be tested for errors. erase suspend status (bit 6). the erase sus- pend status bit indicates that an erase operation has been suspended or is going to be suspended. when the erase suspend status bit is high (set to 1), a program/erase suspend command has been issued and the memory is waiting for a pro- gram/erase resume command. the erase suspend status should only be consid- ered valid when the program/erase controller sta- tus bit is high (program/erase controller inactive). bit 7 is set within 30s of the program/erase sus- pend command being issued therefore the memo- ry may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status (bit 5). the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. when the erase status bit is high (set to 1), the program/ erase controller has applied the maximum num- ber of pulses to the block and still failed to verify that the block has erased correctly. the erase sta- tus bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status (bit 4). the program status bit is used to identify a program failure. when the program status bit is high (set to 1), the pro- gram/erase controller has applied the maximum number of pulses to the byte and still failed to ver- ify that it has programmed correctly. the program status bit should be read once the program/erase controller status bit is high (program/erase con- troller inactive). once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new command is issued, otherwise the new command will appear to fail. v ppf status (bit 3). the v ppf status bit can be used to identify an invalid voltage on the v ppf pin during program and erase operations. the v ppf pin is only sampled at the beginning of a program or erase operation. indeterminate results can oc- cur if v ppf becomes invalid during an operation. when the v ppf status bit is low (set to 0), the voltage on the v ppf pin was sampled at a valid voltage; when the v ppf status bit is high (set to 1), the v ppf pin has a voltage that is below the v ppf lockout voltage, v pplk , the memory is pro- tected and program and erase operations cannot be performed. once set high, the v ppf status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program suspend status (bit 2). the program suspend status bit indicates that a program oper- ation has been suspended. when the program suspend status bit is high (set to 1), a program/ erase suspend command has been issued and the memory is waiting for a program/erase re- sume command. the program suspend status should only be considered valid when the pro-
m36w832te, m36w832be 24/64 gram/erase controller status bit is high (program/ erase controller inactive). bit 2 is set within 5s of the program/erase suspend command being is- sued therefore the memory may still complete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status (bit 1). the block pro- tection status bit can be used to identify if a pro- gram or erase operation has tried to modify the contents of a locked block. when the block protection status bit is high (set to 1), a program or erase operation has been at- tempted on a locked block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new command is issued, otherwise the new command will appear to fail. reserved (bit 0). bit 0 of the status register is reserved. its value must be masked. note: refer to appendix c, flowcharts and pseudo codes, for using the status register. table 11. flash status register bits note: logic level '1' is high, '0' is low. bit name logic level definition 7 p/e.c. status '1' ready '0' busy 6 erase suspend status '1' suspended '0' in progress or completed 5 erase status '1' erase error '0' erase success 4 program status '1' program error '0' program success 3 v ppf status '1' v ppf invalid, abort '0' v ppf ok 2 program suspend status '1' suspended '0' in progress or completed 1 block protection status '1' program/erase on protected block, abort '0' no operation to protected blocks 0 reserved
25/64 m36w832te, m36w832be sram operations there are five standard operations that control the sram component. these are bus read, bus write, standby/power-down, data retention and output disable. a summary is shown in table 2, main operation modes read. read operations are used to output the contents of the sram array. the sram is in byte read mode whenever write enable, ws , is at v ih , output enable, gs , is at v il , chip enable, e1s , is at v il , chip enable, e2s, is at v ih , and ubs or lbs is at v il . the sram is in word read mode whenever write enable, ws , is at v ih , output enable, gs , is at v il , byte enable inputs ubs and lbs are both at v il and the two chip enable inputs, e1s , and e2s are dont care. valid data will be available on the output pins after a time of t avqv after the last stable address. if the chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t e1lqv , t e2hqv , or t glqv ) rath- er than the address. data out may be indetermi- nate at t e1lqx , t e2hqx and t glqx , but data lines will always be valid at t avqv (see table 20, figures 14 and 15). write. write operations are used to write data to the sram. the sram is in write mode whenever ws and e1s are at v il , and e2s is at v ih . either the chip enable inputs, e1s and e2s, or the write enable input, ws , must be deasserted during ad- dress transitions for subsequent write cycles. a write operation is initiated when e1s is at v il , e2s is at v ih and ws is at v il . the data is latched o the falling edge of e1s , the rising edge of e2s or the falling edge of ws , whichever occurs last. the write cycle is terminated on the rising edge of e1s , the rising edge of ws or the falling edge of e2s, whichever occurs first. if the output is enabled (e1s =v il , e2s=v ih and gs =v il ), then ws will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. the data input must be valid for t d- vwh before the rising edge of write enable, for t dve1h before the rising edge of e1s or for t dve2l before the falling edge of e2s, whichever occurs first, and remain valid for t whdx , t e1hax or t e2lax (see table 21, figure 17, 18, 19 and 20). standby/power-down. the sram component has a chip enabled power-down feature which in- vokes an automatic standby mode (see table 20 and figure 16). the sram is in standby mode whenever either chip enable is deasserted, e1s at v ih or e2s at v il . data retention. the sram data retention per- formance as v dds goes down to v dr are de- scribed in table 22, figures 21 and 22, sram low v dds data retention ac waveforms, e1s controlled and sram low v dds data retention ac waveforms, e2s controlled, respectively. output disable. the data outputs are high im- pedance when the output enable, gs , is at v ih with write enable, ws , at v ih .
m36w832te, m36w832be 26/64 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 12. absolute maximum ratings note: 1. depends on range. symbol parameter value unit min max t a ambient operating temperature (1) C40 85 c t bias temperature under bias C40 125 c t stg storage temperature C55 150 c v io input or output voltage C0.5 v ddqf +0.5 v v ddf , v ddqf flash supply voltage C0.6 4.1 v v ppf program voltage C0.6 13 v v dds sram supply voltage C0.5 3.6 v
27/64 m36w832te, m36w832be dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 13, operating and ac measurement conditions. de- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. the operating and ac measurement parameters given below (see table 13, operating and ac measurement conditions) are those of the stand- alone flash and sram devices and some differ from those of the stacked product. table 13. operating and ac measurement conditions figure 8. ac measurement i/o waveform note: v ddq means v ddqf = v dds figure 9. ac measurement load circuit table 14. device capacitance note: sampled only, not 100% tested. parameter sram flash memory units 70 70 / 85 min max min max v ddf supply voltage C C 2.7 3.6 v v ddqf supply voltage C C 2.7 3.6 v v dds supply voltage 2.7 3.3 C C v ambient operating temperature C 40 85 C 40 85 c load capacitance (c l ) 50 50 pf input rise and fall times 3.3 5 ns input pulse voltages 0 to v ddqf 0 to v ddqf v input and output timing ref. voltages v ddqf /2 v ddqf /2 v ai90166 v ddq 0v v ddq /2 ai90167 v ddqf c l c l includes jig capacitance 25k w device under test 0.1f v ddf 0.1f v ddqf 25k w symbol parameter test condition max unit c in input capacitance v in = 0v, f=1 mhz 12 pf c out output capacitance v out = 0v, f=1 mhz 16 pf
m36w832te, m36w832be 28/64 table 15. dc characteristics symbol parameter device test condition min typ max unit i li input leakage current flash & sram 0v v in v ddqf 2 a i lo output leakage current flash 0v v out v ddqf, 10 a sram 0v v out v ddqf, sram outputs hi-z 1 a i dds v dd standby current flash ef = v ddqf 0.2v v ddqf = v ddf max 15 50 a sram e1s 3 v dds C 0.3v or e2s 0.3v v in 3 v dds C 0.3v or v in 0.3v f = f max (address and data inputs only) f = 0 (gs , ws , ubs and lbs ) 825a e1s 3 v dds C 0.3v or e2s 0.3v v in 3 v dds C 0.3v or v in 0.3v f = 0, v dds = v dds max 825a i ddd supply current (reset) flash rpf = v ssf 0.2v 15 50 a i dd supply current sram v out = 0ma f = f max = 1/t avav , cmos levels v dds = v dds max 715ma i out = 0 ma, f = 1mhz, cmos levels 12ma i ddr supply current (read) flash ef = v il , gf = v ih, f = 5 mhz 918ma i ddw supply current (program) flash program in progress v ppf = 12v 5% 510ma program in progress v ppf = v ddf 10 20 ma i dde supply current (erase) flash erase in progress v ppf = 12v 5% 520ma erase in progress v ppf = v ddf 10 20 ma i ddes supply current (program/erase suspend) flash e f = v ddqf 0.2v, erase suspended 15 50 a i pp program current (read or standby) flash v ppf > v ddf 400 a i pp1 v ppf v ddf 15a i pp2 program current (reset) flash rp f = v ssf 0.2v 15a i ppw program current (program) flash program in progress v ppf = 12v 5% 110ma program in progress v ppf = v ddf 15a
29/64 m36w832te, m36w832be i ppe program current (erase) flash erase in progress v ppf = 12v 5% 310ma erase in progress v ppf = v ddf 15a v il input low voltage flash & sram v ddqf = v dds 3 2.7v C0.3 0.8 v v ih input high voltage flash & sram v ddqf = v dds 3 2.7v 0.7v dd qf v ddqf +0.4 v v ol output low voltage flash & sram v ddqf = v dds = v dd min i ol = 100a 0.1 v v oh output high voltage flash & sram v ddqf = v dds = v dd min i oh = C100a 2.4 v v ppl program voltage (program or erase operations) flash 1.65 3.6 v v pph program voltage (program or erase operations) flash 11.4 12.6 v v pplk program voltage (program and erase lock-out) flash 1 v v lko v ddf supply voltage (program and erase lock-out) flash 2 v symbol parameter device test condition min typ max unit
m36w832te, m36w832be 30/64 figure 10. flash read mode ac waveforms table 16. flash read ac characteristics note: 1. sampled only, not 100% tested. 2. gf may be delayed by up to t elqv - t glqv after the falling edge of ef without increasing t elqv . symbol alt parameter flash device unit 70 85 t avav t rc address valid to next address valid min 70 85 ns t av qv t acc address valid to output valid max 70 85 ns t axqx (1) t oh address transition to output transition min 0 0 ns t ehqx (1) t oh chip enable high to output transition min 0 0 ns t ehqz (1) t hz chip enable high to output hi-z max 20 20 ns t elqv (2) t ce chip enable low to output valid max 70 85 ns t elqx (1) t lz chip enable low to output transition min 0 0 ns t ghqx (1) t oh output enable high to output transition min 0 0 ns t ghqz (1) t df output enable high to output hi-z max 20 20 ns t glqv (2) t oe output enable low to output valid max 20 20 ns t glqx (1) t olz output enable low to output transition min 0 0 ns dq0-dq15 ai90168b a0-a20 ef gf valid taxqx tavav valid tavqv telqv telqx tglqv tglqx addr. valid chip enable outputs enabled data valid standby tghqx tghqz tehqx tehqz
31/64 m36w832te, m36w832be figure 11. flash write ac waveforms, write enable controlled ef gf wf dq0-dq15 v ppf a0-a20 ai90169b wpf command cmd or data status register valid tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv twphwh twhgl tqvwpl twhel
m36w832te, m36w832be 32/64 table 17. flash write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. 2. applicable if v ppf is seen as a logic input (v ppf < 3.6v). symbol alt parameter flash device unit 70 85 t avav t wc write cycle time min 70 85 ns t av wh t as address valid to write enable high min 45 45 ns t dvwh t ds data valid to write enable high min 45 45 ns t elwl t cs chip enable low to write enable low min 0 0 ns t elqv chip enable low to output valid min 70 85 ns t qvvpl (1,2) output valid to v ppf low min 0 0 ns t qvwpl output valid to write protect low min 0 0 ns t vphwh (1) t vps v ppf high to write enable high min 200 200 ns t whax t ah write enable high to address transition min 0 0 ns t whdx t dh write enable high to data transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whel write enable high to chip enable low min 25 25 ns t whgl write enable high to output enable low min 20 20 ns t whwl t wph write enable high to write enable low min 25 25 ns t wlwh t wp write enable low to write enable high min 45 45 ns t wphwh write protect high to write enable high min 45 45 ns
33/64 m36w832te, m36w832be figure 12. flash write ac waveforms, chip enable controlled ef gf dq0-dq15 v ppf a0-a20 ai90170b wf wpf command cmd or data status register valid tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh power-up and set-up command confirm command or data input status register read 1st polling telqv twpheh tehgl tqvwpl
m36w832te, m36w832be 34/64 table 18. flash write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. 2. applicable if v ppf is seen as a logic input (v ppf < 3.6v). symbol alt parameter flash device unit 70 85 t avav t wc write cycle time min 70 85 ns t ave h t as address valid to chip enable high min 45 45 ns t dveh t ds data valid to chip enable high min 45 45 ns t ehax t ah chip enable high to address transition min 0 0 ns t ehdx t dh chip enable high to data transition min 0 0 ns t ehel t cph chip enable high to chip enable low min 25 25 ns t ehgl chip enable high to output enable low min 25 25 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t eleh t cp chip enable low to chip enable high min 45 45 ns t elqv chip enable low to output valid min 70 85 ns t qvvpl (1,2) output valid to v ppf low min 0 0 ns t qvwpl data valid to write protect low min 0 0 ns t vpheh (1) t vps v ppf high to chip enable high min 200 200 ns t wlel t cs write enable low to chip enable low min 0 0 ns t wpheh write protect high to chip enable high min 45 45 ns
35/64 m36w832te, m36w832be figure 13. flash power-up and reset ac waveforms table 19. flash power-up and reset ac characteristics note: 1. the device reset is possible but not guaranteed if t plph < 100ns. 2. sampled only, not 100% tested. 3. it is important to assert rpf in order to allow proper cpu initialization during power up or reset. symbol parameter test condition flash device unit 70 85 t phwl t phel t phgl reset high to write enable low, chip enable low, output enable low during program and erase min 50 50 s others min 30 30 ns t plph (1,2) reset low to reset high min 100 100 ns t vdhph (3) supply voltages high to reset high min 50 50 s ai90171 wf, rpf tphwl tphel tphgl ef, gf vddf, vddqf tvdhph tphwl tphel tphgl tplph power-up reset
m36w832te, m36w832be 36/64 figure 14. sram read mode ac waveforms, address controlled with ubs = lbs = v il note: e1s = low, e2s = high, gs = low, ws = high. figure 15. sram read ac waveforms, gs controlled note: write enable (ws ) = high. address valid prior to or at the same time as e1s goes low and e2s goes high. figure 16. sram standby ac waveforms ai90180 tavav tavqv taxqx a0-a18 dq0-dq15 valid data valid data valid ai07965 tavav te1lqv te1hqz tglqv tglqx tghqz data valid a0-a18 e1s gs dq0-dq15 te2hqv valid te2lqz e2s te1lqx te2hqx v dds tpu 50% 50% tpd ai07985 tpd e2s i dd tpu 50% e1s i dds
37/64 m36w832te, m36w832be table 20. sram read ac characteristics note: 1. sampled only. not 100% tested. figure 17. sram write ac waveforms, e1 s or e2s controlled note: 1. dq0-dq15 are high impedance if gs = v ih . 2. if e1s or e2s and ws are deasserted at the same time, dq0-dq15 remain high impedance. symbol alt parameter sram unit min max t avav t rc read cycle time 70 ns t av qv t acc address valid to output valid 70 ns t axqx t oh address transition to output transition 10 ns t e1hqz t e2lqz t chz1 chip enable 1 high to output hi-z 25 ns t e1lqv t e2hqv t acs1 chip enable 1 low or chip enable 2 high to output valid 70 ns t e1lqx t e2hqx t clz1 chip enable 1 low to output transition 10 ns t ghqz t ohz output enable high to output hi-z 25 ns t glqv t oe output enable low to output valid 35 ns t glqx t olz output enable low to output transition 5 ns t pd (1) chip enable 1 high or chip enable 2 low to power down 70 ns t pu (1) chip enable 1 low or chip enable 2 high to power up 0 ns ai07966 tavav te1hax tdve1h tdve2l input valid a0-a18 e1s ws dq0-dq15 address valid e2s tave1h tave2l twle1h twle2l te1hdz te2ldz tave1l te2he2l te1le1h tave2h te2lax
m36w832te, m36w832be 38/64 figure 18. sram write ac waveforms, ws controlled, gs high during write note: 1. dq0-dq15 are high impedance if gs = v ih . 2. if e1s or e2s and ws are deasserted at the same time, dq0-dq15 remain high impedance. figure 19. sram write ac waveforms, ws controlled with gs low note: 1. if e1s , e2s and ws are deasserted at the same time, dq0-dq15 remain high impedance. 2. the minimum write cycle time (t avav ) is the sum of t wlqz and t dvwh . 3. during this period, the i/o pins are in output mode and input signals should not be applied. ai07967 tavav twhax tdvwh input valid a0-a18 e1s ws dq0-dq15 valid e2s tavwh tghqz twhdz tavwl te2hwh te1lwh gs twlwh note 2 ai07968 tavav twhax tdvwh input valid a0-a18 e1s ws dq0-dq15 valid e2s tavwh twlwh tavwl twhdz twhqx te1lwh te2hwh twlqz note 3
39/64 m36w832te, m36w832be figure 20. sram write cycle waveform, ubs and lbs controlled gs low, note: 1. during this period, the i/o pins are in output mode and input signals should not be applied. ai07969 tavav tbhax tdvbh input valid a0-a18 e1s ws dq0-dq15 valid e2s tavbh tavwl tbhdz tblbh ubs, lbs note 1 twlqz tbhqx
m36w832te, m36w832be 40/64 table 21. sram write ac characteristics symbol alt parameter sram unit min max t avav t wc write cycle time 70 ns t av e1l , t ave 2h , t avwl, t as address valid to beginning of write 0 ns t ave 1h , t ave2l t av bh t aw address valid to chip enable 1 low or chip enable 2 high 60 ns t av wh t aw address valid to write enable high 60 ns t blbh t bw ub s , lb s low to ub s , lb s high 60 ns t dve1h , t dve2l , t dvwh t dvbh t dw input valid to end of write 30 ns t e1hax , t e2lax , t whax t bhax t wr end of write to address change 0 ns t e1hdz , t e2ldz , t whdz t bhdz t hd address transition to end of write 0 ns t e1le1h, t e1lwh t cw1 chip enable 1 low to end of write 60 ns t e2he2l, t e2hwh t cw2 chip enable 2 high to end of write 60 ns t ghqz t ghz output enable high to output hi-z 25 ns t whqx t bhqx t dh write enable high to input transition 10 ns t wlqz t whz write enable low to output hi-z 20 ns t wlwh t wle1h t wle2l t wp write enable pulse width 50 ns
41/64 m36w832te, m36w832be figure 21. sram low v dds data retention ac waveforms, e1s controlled figure 22. sram low v dds data retention ac waveforms, e2s controlled table 22. sram low v dds data retention characteristic note: 1. sampled only. not 100% tested. symbol parameter test condition min typ max unit i dddr supply current (data retention) v dds = 1.5v, e1s 3 v dds C 0.3v, v in 3 v dds C 0.3v or v in 0.3v no input may exceed v dds + 0.3v 420a v dr supply voltage (data retention) 1.5 3.3 v t cdr chip disable to power down 0 ns t r operation recovery time 70 ns ai07970 e1s tcdr v dds tr data retention mode v dds (min) v dds (min) v dr > 1.5v e1s > v dds - 0.3v and e2s < 0.3v or e2s > v dds - 0.3v ai07982 e2s tcdr v dds tr data retention mode v dds (min) v dds (min) v dr > 1.5v e2s < 0.3v
m36w832te, m36w832be 42/64 package mechanical figure 23. stacked lfbga66 12x8mm, 8x8 array, 0.8mm pitch, bottom view package outline note: drawing is not to scale. table 23. stacked lfbga66, 12x8mm, 8x8 ball array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.400 0.0551 a1 0.300 0.0118 a2 1.100 0.0433 b 0.400 0.300 0.500 0.0157 0.0118 0.0197 d 12.000 C C 0.4724 C C d1 5.600 C C 0.2205 C C d2 8.800 C C 0.3465 C C ddd 0.100 0.0039 e 8.000 C C 0.3150 C C e1 5.600 C C 0.2205 C C e 0.800 C C 0.0315 C C fd 1.600 C C 0.0630 C C fe 1.200 C C 0.0472 C C sd 0.400 C C 0.0157 C C se 0.400 C C 0.0157 C C a2 a1 a bga-z12 ddd d e e b se fd fe e1 e d1 sd d2 ball "a1"
43/64 m36w832te, m36w832be figure 24. stacked lfbga66 daisy chain - package connections (top view through package) ai90172b d c 12 11 10 9 8 3 e f a b h g 7 6 5 4 12
m36w832te, m36w832be 44/64 figure 25. stacked lfbga66 daisy chain - pcb connections proposal (top view through package) 1 ai90173b d c e f a b h g start point end point 12 11 10 9 8 37 6 5 4 2
45/64 m36w832te, m36w832be part numbering table 24. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. table 25. daisy chain ordering scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. example: m36 w 8 32t e 70 za 6 t device type m36 = mmp (flash + sram) operating voltage w = v ddf = 2.7v to 3.3v, v dds = v ddqf = 2.7v to 3.3v sram chip size & organization 8 = 8 mbit (512kb x 16 bit) flash chip size & organization 32t = 32 mbit (x16), boot block, top configuration 32b = 32 mbit (x16), boot block, bottom configuration sram component e = 8mb, 0.16m, 70ns, 3.0v speed 70 = 70ns 85 = 85ns package za = lfbga66: 12x8mm, 0.8mm pitch temperature range 1 = 0 to 70c 6 = C40 to 85c option t = tape & reel packing s = special tape example: m36w832te -za t device type m36w832te daisy chain -za = lfbga66: 12x8mm, 0.8mm pitch option t = tape & reel packing
m36w832te, m36w832be 46/64 appendix a. flash memory block address tables table 26. top boot block addresses, m36w832te # size (kword) address range 0 4 1ff000-1fffff 1 4 1fe000-1fefff 2 4 1fd000-1fdfff 3 4 1fc000-1fcfff 4 4 1fb000-1fbfff 5 4 1fa000-1fafff 6 4 1f9000-1f9fff 7 4 1f8000-1f8fff 8 32 1f0000-1f7fff 9 32 1e8000-1effff 10 32 1e0000-1e7fff 11 32 1d8000-1dffff 12 32 1d0000-1d7fff 13 32 1c8000-1cffff 14 32 1c0000-1c7fff 15 32 1b8000-1bffff 16 32 1b0000-1b7fff 17 32 1a8000-1affff 18 32 1a0000-1a7fff 19 32 198000-19ffff 20 32 190000-197fff 21 32 188000-18ffff 22 32 180000-187fff 23 32 178000-17ffff 24 32 170000-177fff 25 32 168000-16ffff 26 32 160000-167fff 27 32 158000-15ffff 28 32 150000-157fff 29 32 148000-14ffff 30 32 140000-147fff 31 32 138000-13ffff 32 32 130000-137fff 33 32 128000-12ffff 34 32 120000-127fff 35 32 118000-11ffff 36 32 110000-117fff 37 32 108000-10ffff 38 32 100000-107fff 39 32 0f8000-0fffff 40 32 0f00000-f7fff 41 32 0e8000-0effff 42 32 0e0000-0e7fff 43 32 0d8000-0dffff 44 32 0d0000-0d7fff 45 32 0c8000-0cffff 46 32 0c0000-0c7fff 47 32 0b8000-0bffff 48 32 0b0000-0b7fff 49 32 0a8000-0affff 50 32 0a0000-0a7fff 51 32 098000-09ffff 52 32 090000-097fff 53 32 088000-08ffff 54 32 080000-087fff 55 32 078000-07ffff 56 32 070000-077fff 57 32 068000-06ffff 58 32 060000-067fff 59 32 058000-05ffff 60 32 050000-057fff 61 32 048000-04ffff 62 32 040000-047fff 63 32 038000-03ffff 64 32 030000-037fff 65 32 028000-02ffff 66 32 020000-027fff 67 32 018000-01ffff 68 32 010000-017fff 69 32 008000-00ffff 70 32 000000-007fff
47/64 m36w832te, m36w832be table 27. bottom boot block addresses, m36w832be # size (kword) address range 70 32 1f8000-1fffff 69 32 1f0000-1f7fff 68 32 1e8000-1effff 67 32 1e0000-1e7fff 66 32 1d8000-1dffff 65 32 1d0000-1d7fff 64 32 1c8000-1cffff 63 32 1c0000-1c7fff 62 32 1b8000-1bffff 61 32 1b0000-1b7fff 60 32 1a8000-1affff 59 32 1a0000-1a7fff 58 32 198000-19ffff 57 32 190000-197fff 56 32 188000-18ffff 55 32 180000-187fff 54 32 178000-17ffff 53 32 170000-177fff 52 32 168000-16ffff 51 32 160000-167fff 50 32 158000-15ffff 49 32 150000-157fff 48 32 148000-14ffff 47 32 140000-147fff 46 32 138000-13ffff 45 32 130000-137fff 44 32 128000-12ffff 43 32 120000-127fff 42 32 118000-11ffff 41 32 110000-117fff 40 32 108000-10ffff 39 32 100000-107fff 38 32 0f8000-0fffff 37 32 0f0000-0f7fff 36 32 0e8000-0effff 35 32 0e0000-0e7fff 34 32 0d8000-0dffff 33 32 0d0000-0d7fff 32 32 0c8000-0cffff 31 32 0c0000-0c7fff 30 32 0b8000-0bffff 29 32 0b0000-0b7fff 28 32 0a8000-0affff 27 32 0a0000-0a7fff 26 32 098000-09ffff 25 32 090000-097fff 24 32 088000-08ffff 23 32 080000-087fff 22 32 078000-07ffff 21 32 070000-077fff 20 32 068000-06ffff 19 32 060000-067fff 18 32 058000-05ffff 17 32 050000-057fff 16 32 048000-04ffff 15 32 040000-047fff 14 32 038000-03ffff 13 32 030000-037fff 12 32 028000-02ffff 11 32 020000-027fff 10 32 018000-01ffff 9 32 010000-017fff 8 32 008000-00ffff 7 4 007000-007fff 6 4 006000-006fff 5 4 005000-005fff 4 4 004000-004fff 3 4 003000-003fff 2 4 002000-002fff 1 4 001000-001fff 0 4 000000-000fff
m36w832te, m36w832be 48/64 appendix b. common flash interface (cfi) the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. tables 28, 29, 30, 31, 32 and 33 show the addresses used to re- trieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see table 33, security code area). this area can be accessed only in read mode by the final user. it is impossible to change the security num- ber after it has been written by st. issue a read command to return to read mode. table 28. query structure overview note: query data are always presented on the lowest order data outputs. table 29. cfi query identification string note: query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are 0. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) offset data description value 00h 0020h manufacturer code st 01h 88bah 88bbh device code to p bottom 02h-0fh reserved reserved 10h 0051h "q" 11h 0052h query unique ascii string "qry" "r" 12h 0059h "y" 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm intel compatible 14h 0000h 15h 0035h address for primary algorithm extended query table (see table 31) p = 35h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (0000h means none exists) na 18h 0000h 19h 0000h address for alternate algorithm extended query table (0000h means none exists) na 1ah 0000h
49/64 m36w832te, m36w832be table 30. cfi query system interface information offset data description value 1bh 0027h v ddf logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 2.7v 1ch 0036h v ddf logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 3.6v 1dh 00b4h v ppf [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 11.4v 1eh 00c6h v ppf [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12.6v 1fh 0004h typical time-out per single word program = 2 n s 16s 20h 0004h typical time-out for double/ quadruple word program = 2 n s 16s 21h 000ah typical time-out per individual block erase = 2 n ms 1s 22h 0000h typical time-out for full chip erase = 2 n ms na 23h 0005h maximum time-out for word program = 2 n times typical 512s 24h 0005h maximum time-out for double/ quadruple word program = 2 n times typical 512s 25h 0003h maximum time-out per individual block erase = 2 n times typical 8s 26h 0000h maximum time-out for chip erase = 2 n times typical na
m36w832te, m36w832be 50/64 table 31. device geometry definition offset word mode data description value 27h 0016h device size = 2 n in number of bytes 4 mbyte 28h 29h 0001h 0000h flash device interface code description x16 async. 2ah 2bh 0003h 0000h maximum number of bytes in multi-byte program or page = 2 n 8 2ch 0002h number of erase block regions within the device. it specifies the number of regions within the device containing contiguous erase blocks of the same size. 2 m28w320ect 2dh 2eh 003eh 0000h region 1 information number of identical-size erase block = 003eh+1 63 2fh 30h 0000h 0001h region 1 information block size in region 1 = 0100h * 256 byte 64 kbyte 31h 32h 0007h 0000h region 2 information number of identical-size erase block = 0007h+1 8 33h 34h 0020h 0000h region 2 information block size in region 2 = 0020h * 256 byte 8 kbyte m28w320ecb 2dh 2eh 0007h 0000h region 1 information number of identical-size erase block = 0007h+1 8 2fh 30h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 byte 8 kbyte 31h 32h 003eh 0000h region 2 information number of identical-size erase block = 003eh=1 63 33h 34h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 byte 64 kbyte
51/64 m36w832te, m36w832be table 32. primary algorithm-specific extended query table note: 1. see table 29, offset 15 for p pointer definition. offset p = 35h (1) data description value (p+0)h = 35h 0050h primary algorithm extended query table unique ascii string pri "p" (p+1)h = 36h 0052h "r" (p+2)h = 37h 0049h "i" (p+3)h = 38h 0031h major version number, ascii "1" (p+4)h = 39h 0030h minor version number, ascii "0" (p+5)h = 3ah 0066h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported (1 = yes, 0 = no) bit 1 suspend erase supported (1 = yes, 0 = no) bit 2 suspend program supported (1 = yes, 0 = no) bit 3 legacy lock/unlock supported (1 = yes, 0 = no) bit 4 queued erase supported (1 = yes, 0 = no) bit 5 instant individual block locking supported (1 = yes, 0 = no) bit 6 protection bits supported (1 = yes, 0 = no) bit 7 page mode read supported (1 = yes, 0 = no) bit 8 synchronous read supported (1 = yes, 0 = no) bit 31 to 9 reserved; undefined bits are 0 no ye s ye s no no ye s ye s no no (p+6)h = 3bh 0000h (p+7)h = 3ch 0000h (p+8)h = 3dh 0000h (p+9)h = 3eh 0001h supported functions after suspend read array, read status register and cfi query are always supported during erase or program operation bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are 0 yes (p+a)h = 3fh 0003h block lock status defines which bits in the block status register section of the query are implemented. address (p+a)h contains less significant byte bit 0 block lock status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are 0 ye s ye s (p+b)h = 40h 0000h (p+c)h = 41h 0030h v ddf logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 3v (p+d)h = 42h 00c0h v ppf supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12v (p+e)h = 43h 0001h number of protection register fields in jedec id space. "00h," indicates that 256 protection bytes are available 01 (p+f)h = 44h 0080h protection field 1: protection description this field describes user-available. one time programmable (otp) protection register bytes. some are pre-programmed with device unique serial numbers. others are user programmable. bits 0C15 point to the protection register lock byte, the sections first byte. the following bytes are factory pre-programmed and user-programmable. bit 0 to 7 lock/bytes jedec-plane physical low address bit 8 to 15 lock/bytes jedec-plane physical high address bit 16 to 23 "n" such that 2 n = factory pre-programmed bytes bit 24 to 31 "n" such that 2 n = user programmable bytes 80h (p+10)h = 45h 0000h 00h (p+11)h = 46h 0003h 8 byte (p+12)h = 47h 0003h 8 byte (p+13)h = 48h reserved
m36w832te, m36w832be 52/64 table 33. security code area offset data description 80h 00xx protection register lock 81h xxxx 64 bits: unique device number 82h xxxx 83h xxxx 84h xxxx 85h xxxx 128 bits: user programmable otp 86h xxxx 87h xxxx 88h xxxx 89h xxxx 8ah xxxx 8bh xxxx 8ch xxxx
53/64 m36w832te, m36w832be appendix c. flash memory flowcharts and pseudo codes figure 26. program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v ppf invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. ai90174b write 40h or 10h start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v ppf invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (any_address, 0x40) ; /*or writetoflash (any_address, 0x10) ; */ do { status_register=readflash (any_address) ; /* ef or gf must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*v ppf invalid error */ error_handler ( ) ; yes end yes no b1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
m36w832te, m36w832be 54/64 figure 27. double word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v ppf invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 and address 2 must be consecutive addresses differing only for bit a0. ai90175b write 30h start write address 1 & data 1 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v ppf invalid error (1, 2) program error (1, 2) yes end yes no b1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) double_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2) { writetoflash (any_address, 0x30) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (any_address) ; /* ef or gf must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*v ppf invalid error */ error_handler ( ) ; if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
55/64 m36w832te, m36w832be figure 28. quadruple word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v ppf invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase operations. 3. address 1 to address 4 must be consecutive addresses differing only for bits a0 and a1. write 56h ai07950 start write address 1 & data 1 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v ppf invalid error (1, 2) program error (1, 2) yes end yes no b1 = 0 program to protected block error (1, 2) write address 2 & data 2 (3) quadruple_word_program_command (addresstoprogram1, datatoprogram1, addresstoprogram2, datatoprogram2, addresstoprogram3, datatoprogram3, addresstoprogram4, datatoprogram4) { writetoflash (any_address, 0x56) ; writetoflash (addresstoprogram1, datatoprogram1) ; /*see note (3) */ writetoflash (addresstoprogram2, datatoprogram2) ; /*see note (3) */ writetoflash (addresstoprogram3, datatoprogram3) ; /*see note (3) */ writetoflash (addresstoprogram4, datatoprogram4) ; /*see note (3) */ /*memory enters read status state after the program command*/ do { status_register=readflash (any_address) ; /* ef or gf must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*v ppf invalid error */ error_handler ( ) ; if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; } write address 3 & data 3 (3) write address 4 & data 4 (3)
m36w832te, m36w832be 56/64 figure 29. program suspend & resume flowchart and pseudo code ai90176b write 70h read status register yes no b7 = 1 yes no b2 = 1 program continues write d0h read data from another address start write b0h program complete write ffh read data program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (any_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (any_address) ; /* ef or gf must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b2==0) /*program completed */ { writetoflash (any_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (any_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ } } write ffh
57/64 m36w832te, m36w832be figure 30. erase flowchart and pseudo code note: if an error is found, the status register must be cleared before further program/erase operations. ai90177b write 20h start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 yes b4, b5 = 1 v ppf invalid error (1) command sequence error (1) no no b5 = 0 erase error (1) end yes no b1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (any_address, 0x20) ; writetoflash (blocktoerase, 0xd0) ; /* only a12-a20 are significannt */ /* memory enters read status state after the erase command */ } while (status_register.b7== 0) ; do { status_register=readflash (any_address) ; /* ef or gf must be toggled*/ if (status_register.b3==1) /*v ppf invalid error */ error_handler ( ) ; if ( (status_register.b4==1) && (status_register.b5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.b5==1) ) /* erase error */ error_handler ( ) ; }
m36w832te, m36w832be 58/64 figure 31. erase suspend & resume flowchart and pseudo code ai90178b write 70h read status register yes no b7 = 1 yes no b6 = 1 erase continues write d0h read data from another block or program/protection program or block protect/unprotect/lock start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (any_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (any_address) ; /* ef or gf must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b6==0) /*erase completed */ { writetoflash (any_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (any_address, 0xff) ; read_program_data ( ); /*read or program data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume erase*/ } }
59/64 m36w832te, m36w832be figure 32. locking operations flowchart and pseudo code write 01h, d0h or 2fh ai90179 read status register yes no locking change confirmed? start write 60h locking_operation_command (address, lock_operation) { writetoflash (any_address, 0x60) ; /*configuration setup*/ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (any_address, 0xff) ; /*reset to read array mode*/ } write ffh write 90h end if (lock_operation==protect) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unprotect) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (any_address, 0x90) ;
m36w832te, m36w832be 60/64 figure 33. protection register program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v ppf invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. write c0h ai07951 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v ppf invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (any_address, 0xc0) ; do { status_register=readflash (any_address) ; /* ef or gf must be toggled*/ } while (status_register.b7== 0) ; if (status_register.b3==1) /*v ppf invalid error */ error_handler ( ) ; yes end yes no b1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.b4==1) /*program error */ error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; }
61/64 m36w832te, m36w832be appendix d. flash memory command interface and program/erase controller state table 34. write state machine current/next, sheet 1 of 2 note: cmd = command, elect.sg. = electronic signature, ers = erase, prog. = program, prot = protection, sus = suspend. current state sr bit 7 data when read command input (and next state) read array (ffh) program setup (10/40h) erase setup (20h) erase confirm (d0h) prog/ers suspend (b0h) prog/ers resume (d0h) read status (70h) clear status (50h) read array 1 array read array prog.setup ers. setup read array read sts. read array read status 1 status read array program setup erase setup read array read status read array read elect.sg. 1 electronic signature read array program setup erase setup read array read status read array read cfi query 1 cfi read array program setup erase setup read array read status read array lock setup 1 status lock command error lock (complete) lock cmd error lock (complete) lock command error lock cmd error 1 status read array program setup erase setup read array read status read array lock (complete) 1 status read array program setup erase setup read array read status read array prot. prog. setup 1 status protection register program prot. prog. (continue) 0 status protection register program continue prot. prog. (complete) 1 status read array program setup erase setup read array read status read array prog. setup 1 status program program (continue) 0 status program (continue) prog. sus read sts program (continue) prog. sus status 1 status prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array prog. sus read array 1 array prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array prog. sus read elect.sg. 1 electronic signature prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array prog. sus read cfi 1 cfi prog. sus read array program suspend to read array program (continue) prog. sus read array program (continue) prog. sus read sts prog. sus read array program (complete) 1 status read array program setup erase setup read array read status read array erase setup 1 status erase command error erase (continue) erase cmderror erase (continue) erase command error erase cmd.error 1 status read array program setup erase setup read array read status read array erase (continue) 0 status erase (continue) erase sus read sts erase (continue) erase sus read sts 1 status erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase sus read array 1 array erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase sus read elect.sg. 1 electronic signature erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase sus read cfi 1 cfi erase sus read array program setup erase sus read array erase (continue) erase sus read array erase (continue) erase sus read sts erase sus read array erase (complete) 1 status read array program setup erase setup read array read status read array
m36w832te, m36w832be 62/64 table 35. write state machine current/next, sheet 2 of 2 note: cmd = command, elect.sg. = electronic signature, prog. = program, prot = protection. current state command input (and next state) read elect.sg. (90h) read cfi query (98h) lock setup (60h) prot. prog. setup (c0h) lock confirm (01h) lock down confirm (2fh) unlock confirm (d0h) read array read elect.sg. read cfi query lock setup prot. prog. setup read array read status read elect.sg. read cfi query lock setup prot. prog. setup read array read elect.sg. read elect.sg. read cfi query lock setup prot. prog. setup read array read cfi query read elect.sg. read cfi query lock setup prot. prog. setup read array lock setup lock command error lock (complete) lock cmd error read elect.sg. read cfi query lock setup prot. prog. setup read array lock (complete) read elect.sg. read cfi query lock setup prot. prog. setup read array prot. prog. setup protection register program prot. prog. (continue) protection register program (continue) prot. prog. (complete) read elect.sg. read cfi query lock setup prot. prog. setup read array prog. setup program program (continue) program (continue) prog. suspend read status prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) prog. suspend read array prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) prog. suspend read elect.sg. prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) prog. suspend read cfi prog. suspend read elect.sg. prog. suspend read cfi query program suspend read array program (continue) program (complete) read elect.sg. read cfiquery lock setup prot. prog. setup read array erase setup erase command error erase (continue) erase cmd.error read elect.sg. read cfi query lock setup prot. prog. setup read array erase (continue) erase (continue) erase suspend read ststus erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase suspend read array erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase suspend read elect.sg. erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase suspend read cfi query erase suspend read elect.sg. erase suspend read cfi query lock setup erase suspend read array erase (continue) erase (complete) read elect.sg. read cfi query lock setup prot. prog. setup read array
63/64 m36w832te, m36w832be revision history table 36. document revision history date version revision details 16-jul-2002 1.0 first issue 29-nov-2002 2.0 revision history moved to end of document. flash and sram components updated. table 2, main operation modes, modified. flash device: quadruple word program command added, double word program command clarified, v ddqf maximum changed to 3.6v, corrections to table 8, flash program, erase times and program/erase endurance cycles, table 15, dc characteristicss table and to cfi tables 30 and 31. security block removed. command codes table added, dq0, dq2, dq3-dq7 and dq8-dq15 parameters modified for lock in table 7, flash read protection register and lock register. 70ns speed class added. 100ns speed class removed. sram device: data retention on page 25 and sram read and write ac characteristics (figures 14, 15, 16, 17, 18, 19, 20, 21 and 22) modified. figure 7, sram block diagram, added. 24-mar-2003 3.0 document promoted to full datasheet status. minor corrections to sram block diagram. input rise and fall time for 70ns speed class modified in operating and ac measurement conditions table. lfbga connections and daisy chain pin numbers modified. 26-may-2003 3.1 special tape option added to ordering information scheme
m36w832te, m36w832be 64/64 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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